Social Implementation
Kuan-Neng Chen
Specially Appointed Professor
semiconductorselectronic materialselectrical engineering
Biography
Dr. Kuan-Neng Chen received his Ph.D. degree in Electrical Engineering and Computer Science, and his M.S. degree in Materials Science and Engineering, both from Massachusetts Institute of Technology (MIT). Dr. Chen is currently Specially Appointed Professor of Tokyo Institute of Technology, and Distinguished Professor of Department of Electronics Engineering and Vice Dean of International College of Semiconductor Technology in National Chiao Tung University. Prior to the faculty position, he was a Research Staff Member at the IBM Thomas J. Watson Research Center.
Dr. Chen is the recipient of IEEE EPS Exceptional Technical Achievement Award, MOST Outstanding Research Award, NCTU Distinguished Faculty Awards, NCTU Outstanding Industry-Academia Cooperation Achievement Awards, CIE Outstanding Professor Award, CIEE Outstanding Professor Award, and IBM Invention Plateau Invention Achievement Awards. He has authored 280 publications, including 2 books and 6 book chapters, and holds 80 patents. He was Guest Editor of MRS Bulletin. He served as General Co-Chair of IEEE IITC and Program Co-Chair of IEEE IPFA, and committee member of IEDM, IEEE 3DIC, IEEE SSDM, IEEE VLSI-TSA, and IMAPS 3D Packaging. Dr. Chen is a member of Phi Tau Phi Scholastic Honor Society and IEEE Fellow.
Dr. Chen’s current research interests are three-dimensional integrated circuits (3D IC), advanced packaging, and heterogeneous integration.
Expectations for WRHI
The research conducting at WRHI is significant for the exploration of wafer level 3D integration. Both technology development and electrical characterization are my main research topics. Through the research collaboration with faculties at WRHI, with the students from Tokyo Tech and NCTU, I believe many new and important research results can be achieved.
Research Projects
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3D IC、Heterogeneous Integration、Advanced Packaging、Wafer Bonding、TSV
Topics
| 2000 - 2005 | Ph.D., Dept. EECS, MIT |
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| 2005 - 2009 | Research Staff Member, IBM TJ Watson Research Center |
| 2009 - 2012 | Associate Professor, Dept. Electronics Engineering, NCTU |
| 2012 - | Professor, Dept. Electronics Engineering, NCTU |
| 2015 - | Vice Dean, Intl College of Semiconductor Technology, NCTU |
| 2016 - | R&D Director, ITRI |
| 2017- | Specially Appointed Professor, Tokyo Institute of Technology |
| 2018- | Micron Chair Professor
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| 2018- | Distinguished Professor, NCTU |
| 2019- | Vice President, International Affairs, NCTU |
| 2010 | Outstanding Youth Award, Electronics Devices and Materials Association (EDMA), 2010 Young Professor Award, Adventech, 2010 |
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| 2011 | NCTU Distinguished Faculty Award, since 2011 every year NCTU Outstanding Industry-Academia Cooperation Achievement Award |
| 2012 | Outstanding Youth Award, Chinese Institute of Electrical Engineering (CIEE), 2012 NCTU Outstanding Industry-Academia Cooperation Achievement Award |
| 2014 | Outstanding Professor Award, Chinese Institute of Electrical Engineering (CIEE), 2014 Outstanding Service Award, Electronics Devices and Materials Association (EDMA), 2014 NCTU Outstanding Industry-Academia Cooperation Achievement Award |
| 2018 | IEEE Fellow, 2018 |
| 2018 | IEEE EPS Exceptional Technical Achievement Award, IEEE Electronics Packaging Society, 2018. “For contributions to 2.5D and 3D IC heterogeneous integration, with focus on interconnect technologies.”
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| 2018 | MOST Outstanding Research Award, Ministry of Science and Technology, 2018. |
| 2013 | “Through-Silicon-Via Based Double-Side Integrated Microsystem for Neural Sensing Applications”, ISSCC, 2013. |
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| 2014 | “2.5D Heterogeneously Integrated Bio-Sensing Microsystem for Multi-Channel Neural Sensing Applications,” ISSCC, 2014. |
| 2016 | “An Advanced 3D/2.5D Integration Packaging Approach Using Double-Self-Assembly Method with Complex Topography, and Micropin-Fin Heat Sink Interposer for Pressure Sensing System”, IEDM, 2016 “Integration of Neural Sensing Microsystem with TSV-embedded Dissolvable µ-Needles Array, Biocompatible Flexible Interposer, and Neural Recording Circuits”, VLSI, 2016. |
| 2018 | “Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits”, IEDM, 2018. |